1. Field of the Invention
This invention relates generally to memory circuits, and more specifically, to a memory circuit system and architecture for significantly reducing power consumption during stand-by or sleep mode of operation.
2. Discussion of the Prior Art
Negative Word-line (Vwl) generators are used in today""s integrated circuit semiconductor memory chips in order to hold all non-selected word-lines of memory array at a negative potential. The purpose is to reduce cell leakage and improve the retention time. During stand-by, or sleep mode, voltage generators consume energy. One proposal in the art, as described in the reference to D. Takashima, Y. Oowaki et al. entitled xe2x80x9cA Novel Power-Off Mode for a Battery-Backup DRAMxe2x80x9d, Symposium on VLSI Circuits Digest of Technical Papers, 1995, pp. 109-110, is to completely turn this Vwl power off. However, this approach has a disadvantage since the system would take a long period of time, e.g., in the range of 10 xcexcs, to return back to the active mode, or prior to conducting a refresh. This may not be practical, when the eDRAM memory is used and periodical refresh is required. An intuitive approach is to use a lower-power standby pump other than the active pump. Whenever the chip enters the low-power mode, the active pump components are shut off, and only the stand-by pumps remain on to keep the voltage level. This approach however, also has some disadvantages, for example, extra hardware are needed to be built on the expensive chip real estate. These standby pumps are normally weak and not efficient, or less useful during the active mode operation. Besides, these stand-by pumps still consume energy during the low-power mode.
Further, array body bias voltage (Vbb) generators are used in today""s memory chips to supply a voltage for biasing the substrate body in which the active devices are formed. That is, this Vbb voltage is applied to the body of the transfer device of the DRAM array. Vbb is used to block the device sub-threshold leakage by boosting device threshold voltage.
As shown in FIG. 1, each generator 10, Vwl or Vbb, comprises a limiter circuit 12 and an oscillator circuit 15 for generating clock pulse for powering a charge pump circuit 18. The charge pump of each respective generator will then pump the output level 19 of each generator from a first level to a second level. The limiter device 12 is provided to detect whether the output voltage 19 has reached to the targeted second level or not. If it does, then the limiter device 12 will shut off the pump and stop pump operation. Inside each pumps there are at least two boost capacitors (not shown). For example, in a two-stage pump, then about 4 to 6 boost capacitors are presented. These boost caps are used to assist charge pumping. Details of operation are well known to skilled artisans. A decoupling capacitor is also provided for the Vwl generator which is a capacitor connected to its output bus. For example, a 3 nF to 20 nF of decoupling capacitor may be needed for Vwl bus of a DRAM with varying density. It should be understood that the Vbb is the p-WeLL bias voltage, and is already tied to a huge pWell of the DRAM array, therefore, no decoupling capacitor is needed. The decouple capacitor is used to stabilize the output voltage 19 and avoid any coupling effect by other voltage levels.
It would be highly desirable to provide an improved low-power semiconductor memory chip voltage generator design that provides for the switched connection of individual Vbb and Vwl (or Vneg) generators and, the simultaneous turning on of these generators when connected during a power-on operation in order to speed the power on process.
It would additionally be highly desirable to provide an improved, low-power semiconductor memory chip voltage generator design that additionally provides for the separation of switch connected individual Vbb and Vwl (or vneg) generators to avoid any cross-over noise and permit different voltage level outputs during an active mode of operation.
It would additionally be highly desirable to provide an improved low-power semiconductor memory chip voltage generator design that provides for the switched connection of Vbb and Vwl (or Vneg) busses, with the Vwl generator being turned off to save energy during the sleep mode of operation, and obviating the need for a stand-by negative word-line (Vwl) generator system.
It is an object of the present invention to provide an improved low-power semiconductor memory chip voltage generator system that provides for the switched connection of individual Vbb and Vwl (or Vneg) generators and, the simultaneous turning on of these generators when connected during a power-on operation in order to speed the power on process.
It is a further object of the present invention to provide an improved, low-power semiconductor memory chip voltage generator system that additionally provides for the separation of switch connected individual Vbb and Vwl (or Vneg) generators to avoid any cross-over noise and permit different voltage level outputs during an active mode of operation.
It is another object of the present invention to provide an improved low-power semiconductor memory chip voltage generator system that provides for the switched connection of Vbb and Vwl (or Vneg) busses, with the Vwl generator being turned off to save energy during the sleep mode of operation.
It is yet another object of the present invention to provide a low-power voltage supply system for a memory chip device having a relaxed (or longer) sleep refresh duration time so that the energy required during the sleep/refresh may be easily supplied by a Vbb generator pump without causing any disturbance on the array substrate.
According to the invention, there is provided a low-power voltage supply system and method for a memory device comprising a semiconductor substrate array of memory cells, wherein the system comprises: a negative word-line (Vwl) generator device for supplying first (word-line) voltage at an output thereof for selecting memory cells in a memory device; an array body bias voltage (Vbb) generator device for supplying second (back bias) voltage at an output thereof for biasing the substrate array in a memory device; and, a switch device for selectively connecting the negative word-line (Vwl) generator device output to the body bias voltage (Vbb) generator device output during one or more operating states of the memory device.
Preferably, during a power-on operative state for turning on the generator devices, the switch device couples the negative word-line (Vwl) generator device output to the body bias voltage (Vbb) generator device output in order to speed up the power-on process for the memory device.
Additionally, the low-power voltage supply system of the invention provides for the turning off of the negative word-line generator during a sleep/low-power mode of operation, with the switch shorting the negative word-line power supply to the substrate bias (or Vbb) voltage supply which is constantly supported by the Vbb generators. During the low-power mode, although the chip temperature may drop, the memory chip would still consume some energy. For example, the negative word-line level (or Vneg) may drift higher if leakage exists, or a refresh cycle is needed. Therefore, it may not be left floating, or otherwise, the cells may leak if the Vneg becomes less and less negative. On the other hand, the substrate bias (or Vbb) generator is normally left on after the chip is powered on. The voltage level may or may not be identical to the negative word-line level. The Vbb level is determined by the optimum condition in which the cells have lowest leakage level. If Vbb is too high (or less negative), then the sub-threshold leakage level may be poor. But, if Vbb is too low (or more negative), the device junction leakage level will dominate. Nevertheless, the Vbb level is usually tracking with the Vneg level, and most of time their values are identical. Thus, in the active mode, the Vbb and Vneg supplies are separated, so as to avoid any cross-over noise between them. In the active mode, the wordlines may be accessed at a high frequency. As a result, the Vneg level is noisy or fluctuated. If both levels are shorted all the time, the Vbb level will also become noisy which could cause data loss or other unexpected and undesirable effects. This problem is obviated in the sleep mode, since no array activity other than occasional refresh is expected.
Implementation of the low-power voltage generation system and method of the invention are advantageous in that: (1) No extra hardware, e.g. no standby Vneg pumps are needed, which means smaller chip area; (2) A power saving in because Vneg is completely shut off resulting in no (zero) Vneg stand-by energy consumed; (3) No cross-over noise between Vbb and Vneg during the active operating mode since they are isolated, which means less noise; and (4) Design flexibility in that Vbb and Vneg level are enabled to be set slightly different. Furthermore, the principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.